<b>Updated</b> CPU Cheatsheet - Seven Years of Covert CPU Operations

74 Comments

View All Comments

• TrogdorJW - Monday, August 23, 2004 - link

  No problem, Dave - I'm not offended by any means. It's "distributed research" as far as I'm concerned. It's SMP for writers (as long as they're computer geeks, at least).
  
  I of course have only personally dealt with a small fraction of the total number of CPUs, since I have never worked for AMD or Intel. I'm sure there are some employees from those two companies that could provide many missing details if they chose to do so. I have to be honest that I reached the point where I just wasn't seeing any mistakes or ommissions because I had been looking at the charts and data for far too long.
  
  At some point in the coming months, I may look at addressing some of the remaining gaps (i.e. no P3, P2, Duron, or early Athlon CPUs are listed). Until then, I'll simply work on updating the current charts.
  
  One final note: I'm amazed (shocked, even) that there hasn't even been one flame about my terrible Shakespeare parody in the introduction. I did it sort of as a joke, but when my wife looked at it, she groaned in pain. You can thank Kris for removing the Timbuk-3 quote from the conclusion. Hahaha... :D
  
  I've got a busy night (elsewhere), so you'll probably have to wait until after 1 AM PST before I get any real updates to the pages done.

• KristopherKubicki - Monday, August 23, 2004 - link

  The mobile athlons are better refered to as Mobile Athlon 4,
  
  Kristopher

• johnsonx - Monday, August 23, 2004 - link

  Jarred,
  
  I totally agree with your 'aside note'. I hope you didn't take my corrections/addendums as criticism of your effort; if there is to be a 'CPU Cheatsheet', it should be as correct as possible which takes outside input.
  
  BTW, I kept my comments to the desktop/server arena because notebooks often use otherwise unknown variants of chips. If mobile chips are included here, then they should be listed as such. For example, it is true that 133/266 FSB Bartons do exist as Mobile AthlonXP's (and the AthlonMP 2800+ as well), but not as regular AthlonXP's. I've seen other odd variants in notebooks; probably chips meant to satisfy a particular OEM's requirements (like I could swear I've seen a notebook with Mobile AthlonXP 1000+). Then of course if you get into Mobile AXP's, then you've got that tiny uPGA socket-563 to deal with as well. What a mess...
  
  Regarding the 512k Clawhammer vs. Newcastle: I've now gotten the impression that the original OEM 2800+ was (and maybe still is) a Clawhammer, while all the retail ones are Newcastle. My evidence for this theory is that all 3000+ chips are 2.0Ghz, 512k cache; the original ones were 512k Clawhammers and in retail carried the part number ADA3000BOX. The newer ones are Newcastles, and carry the retail part number ADA3000AXBOX. However, the retail 2800+, which came out well after the OEM 2800+, did and still does carry the part number ADA2800BOX. This leads me to conclude that AMD adds the 'AX' when they change cores in the same model number, and further that the retail 2800+ started with the Newcastle core, as the AX has not been added to denote a core change (since I think we all agree that the retail 2800's you can buy today are indeed Newcastles).
  
  Regards,
  
  Dave
  

• silentsnow - Monday, August 23, 2004 - link

  #25, #26
  
  There is a general consensus that all 4AP and 4AR OPN's are 512K ClawHammers. All Rev CG 512KB Athlon's are therefore Newcastle based.

• JarredWalton - Monday, August 23, 2004 - link

  The pipeline stages for Opteron and A64 are indeed 12/17 - that has been corrected, thanks! I had heard that before, but there were quite a few sites that listed it as 10/15 still. I'll have to wait on the other bits (slightly incorrect MHz ranges) until I have a bit more time to spare.
  
  25/26: Yes, there is a socket 754 Newcastle now. AMD is being a little unclear on a lot of the updates, but apparently they can switch the memory controller quite easily in the core, or else the original memory controller was fully capable of dual-channel support but they somehow just turned it off. Anyway, the original 2800+ and 3000+ chips that showed up were, in all likelihood, downgraded Claw Hammer cores.
  
  As an aside note, the power of the Internet is rather impressive. It took a whole lot of time (as I'm sure most of you are aware) to research all the data for this article. Of course, there are bound to be mistakes (as JohnsonX and others have pointed out), but the chance of finding those alone is slim to none. It's like writing a modern software application that doesn't have any bugs! Throw something out on the Internet, however, and with thousands of eyes looking at it, your mistakes are sure to be found. :)
  
  I'll work on verifying and correcting some of the more greivous errors/omissions in the coming day or two. Of course, I'm also working on that little GPU chart... just don't expect die sizes or transistor counts on the chips, as they're very difficult to find. (Not so much the transistor counts, though.)

• NinjaPirate - Monday, August 23, 2004 - link

  On the Intel Cheat Sheet, the Coppermine Celerons are marked as SMP capable, but it is the Mendocino Celerons who are SMP capable. As far as I know, nobody could get Celeron II to run SMP. Anyway, it's a very good article.

• AkumaX - Monday, August 23, 2004 - link

  4. There were no 133Mhz FSB AthlonXP Bartons.
  
  Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.
  
  hehe, trying to keep it to the desktop, i see
  
  also, the Sempron seems to come in Tbred B and Thorton, and the lowest Sempron i've seen is a 2200+ (1.5ghz @ 166mhz fsb)

• wassup4u2 - Monday, August 23, 2004 - link

  I was under the impression that the K7 had a 10-stage int pipeline and a 15 stage fp pipeline, and the one of the changes worked in the K8 was an increase to 12/17 stages, effective starting with the first K8 chip, Sledge Hammer.

• LocutusX - Monday, August 23, 2004 - link

  #25:
  
  "8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct)."
  
  You're 98% right, I believe. The 512k Claw was only sold @ 2.0ghz, and were the "defective" 3200's remarked as 3000+. These were the ones being reviewed around December/January. Most of the new 3000+'s being sold *today*, are of course "true Newcastle". -- AFAIK!
  
  

• johnsonx - Monday, August 23, 2004 - link

  Perhaps these are ticky-tack, but if you want it to be correct:
  
  1. The AthlonXP Palomino was never sold at speeds below 1333Mhz (AthlonXP 1500+).
  
  2. The AthlonMP Palomino was never sold at speeds below 1200Mhz (AthlonMP 1200).
  
  3. The Thoroughbred 'A' core never reached a speed above 1833Mhz (AthlonXP 2200+). To break beyond that, AMD had to switch to the 'B' core.
  
  4. There were no 133Mhz FSB AthlonXP Bartons.
  
  5. The AthlonMP Barton had an FSB of 133, not 166. The only MP chipset, the AMD 760MP/MPX, can only do 133 FSB.
  
  6. The Thoroughbred 'B' core used for the Semprons is the exact same as those used for AthlonXP's, and thus has the same die size, 84mm^2.
  
  7. The Socket-939 AthlonFX is a ClawHammer, not a SledgeHammer. The 'Sledge' requires Registered memory and socket-940.
  
  8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct).
  
  9. You left out the Socket-754 variant of the NewCastle. The Newcastle core starts at 1.8Ghz (S754 2800+), and so far goes up to 2.4Ghz (S754-3400+ and S939-3800+).
  
  Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.